Introduction to DRAMs(Dynamic Random Access Memory) Part 1
The Von Neumann Architecture describes a design architecture for an electronic digital computer. This architecture has been adopted worldwide in building computing systems. The components that make up VNA(Von Neumann Architecture) include:
A Processing unit, Control Unit, Memory, Mass Storage, I/O
When we talk about memory, we talk about the component that stores data and instructions. For the computer to perform operations, it needs instructions and data. eg Add 5 and 6
Here, Add is the instruction while 5, 6 is the data(operands).
DRAM chips are widely used in digital electronics eg. Main Memory (RAM)
DRAM stores each bit of data in a memory cell. A memory cell consists of a transistor and a capacitor.
A transistor is a semiconductor device used to amplify or switch signals and power.
It has 3 terminals: Gate, Source & Drain.
The voltage at the gate controls if current can flow from source to drain. When there’s no voltage on the gate, current is blocked from flowing to the drain from the source. When there’s voltage applied to the gate. The current flows from the source through the transistor to the drain.
To complete a memory cell (unit of storage in a DRAM), A capacitor is attached to the drain.
A capacitor is a device that stores electrical energy by accumulating electric charges on two closely spaced surfaces that are insulated from each other — Wikipedia
Once voltage is applied to the gate, current can flow through the transistor down the drain and charge up the capacitor. The gate is closed leaving the capacitor charged. Once the capacitor is charged we can represent this in binary as 1. To dissipate the charge off the capacitor, we open the transistor gate, once there is no voltage flowing through the source, the stored charge flows from the capacitor out through the source. This state of the capacitor can be represented as a binary 0. This my friend is the fundamental building block of a DRAM memory cell(i.e. basic unit of storage for a bit).
But how do they all come together to store bytes, words etc ?
We combine billions of memory cells together. They’re arranged in a 2D array giving us the ability to access each bit by their index(row, col). Each memory cell is the intersection of a word line and bit line.
The horizontal lines connecting each row are known as word lines while the vertical lines are know as bit lines.
To read a data bit from a memory, we have to introduce extra circuitry know as the sense amplifier.
Sense amplifier is used to detect small signals. In DRAMs, it’s used to amplify the weak signals stored in memory cells
Why do we have weak signals in memory cells ? Why do we need sense amplifiers ?
Remember capacitors store charges ? Over time the charge stored in a capacitor gradually leaks. without intervention, you’d loose the data stored. DRAMs require external memory refresh which periodically rewrites the data stored in the capacitors.
When reading the data, the sense amplifier is able to detect the low charge from the bit line which is stored in the capacitor and raise the voltage to recognizable levels so the data can be interpreted properly. A sense amplifier is connected to each bit line.
To read a bit from a memory cell.
The sense amplifier is disconnected.
Each bit line is pre charged to about half of the voltage supplied. If the volt supplied is 1V, the bit line is charged to 0.5V then the voltage is cut. The bit line has enough capacitance to maintain the voltage for a small amount of time.
The desired word line is then driven high. This applies voltage to all the transistor gates on the word line causing charge to flow from the bit line into the capacitor (when the capacitor isn’t charged) or out(when the capacitor is charged) of the capacitor into the bit line.
With a bit line pre charged to 0.5V, and a capacitor that’s not charged. When the gate is opened by driving the word line high. The volt on the bit line reduces because charge flows into the capacitor (eg. 0.45V). When the capacitor is charged and the gate is opened, the volt on the bit line increases as the charge in the capacitor is dissipated (eg. 0.55V).
The sense amplifier(differential) is able to sense the difference between the original voltage applied to the bit line and the new voltage. The sense amplifier then amplifies the bit line to it’s highest or lowest voltage.
The outputs of the sense amplifier are then latched. This allows the column address to select which latched bit should be outputted to the data bus.
Remember that the storage cells are discharged in a Read operation. To recharge the cells back, based on the outputs of the sense amplifiers that were latched, voltage is applied to each bit line to recharge the memory cells.
When we’re done with the read operation, the word line is switched off which disconnects the storage cell capacitors from the bit lines.
In Part 2, we’d explore how writing to a memory cell is achieved.
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